/*!
 * \file
 */
#ifndef __IRIS404_H__
#define __IRIS404_H__
#include <device/sbdspsoc_sb3500.h>
#include <device/sbdc_sb3500.h>
#include <device/sbarmsoc_sb3500.h>
#include <device/mmioutil.h>
#include <stdlib.h>
#include <stdint.h>

//#include "globals.h"
#include "rf_drv.h"

#define IRIS404_REGISTER_NUMBER               (64)	// Available regs number in iris404 
typedef struct st_iris404mac_row {
    uint32_t                ram_id;                   // ram_id
    uint32_t                ucValue;                  // default value
    uint8_t                 ucType;                   // 0 ->FPGA, 1 ->RegWrite, 2 ->MacWrite, 3->MacMacro, 4 ->MacStart;
} ST_IRIS404MAC_ROW;

typedef struct iris404init
{
	uint16_t id;
	uint32_t init_data;

}IRIS404INIT;

typedef enum
{
  Busy      = 1 << 0,
  LtchRFnE  = 1 << 1,
  LtchRFF   = 1 << 2,
  LtchCFE   = 1 << 3,
  RFEEmpty  = 1 << 4,
  EFFull    = 1 << 5,
  CFEmpty   = 1 << 6,
  CFFull    = 1 << 7,
}SPIx_STATUS_BIT;

/* idle2fdidle config */
extern ST_IRIS404MAC_ROW seq_idle2fdidle[6]; // Cannot define in header file otherwise get multiple definition error

#define INIT_NUM    (2465)       // row num when init. data proc
#define TXPAC_NUM    (685)
#define RXPAC_NUM    (96)
uint32_t    reg_read(uint32_t reg_add);
uint32_t    reg_write(uint32_t reg_add, uint32_t reg_data);

/* register structure in iris404 and ad9361 */
typedef struct st_iris404reg {
    uint8_t                 uiAddr;                         // register address
    uint8_t                 uiDefault;                      // default init. value
    uint8_t                 ucType;                         // register type, 1~3 is available: 1-R; 2-W; 3-R&W; other-undefined;
    uint32_t                ucValue;                        // register value

} ST_IRIS404REG;
#define FAFACTOR                    (33554432)                   // decimal part

#define STAT1_BASE 0x80000F00                               // state register address

#define XSPI_BASE  0x8FC04000                               // base address of SPI

#define NODE_1 1
#define NODE_2 2
#define NODE_3 3

#define TDD_MODE    (0)
#define FDD_MODE	(1)
/*
 * SPI_clk = (HSN_clk/((n+1)*2)), or n = (HSN_clk/(2*SPI_clk)) - 1
 * HSN_clk = 275MHz n=6��then 275MHz/((6+1)*2) = 19.64MHz
 */
// #define SPI_DIV 6
#define SPI_DIV     (24)

#define WRITE_STAT1(__off, __val) \
    (*((volatile unsigned*)(STAT1_BASE | __off)) = (__val))

#define XSPI_WRITE(__node, __off, __val)  \
             MMIO_WRITE32( (XSPI_BASE | (__node<<28)), (__off), (__val) )
#define XSPI_READ(__node, __off)   \
             MMIO_READ32( (XSPI_BASE | (__node<<28)), (__off))

#define wait_ms(__val)              osFastPause((__val)*135000)  // Wait almost 1 ms

#define FREQ                        (30720000)                  // main in-board crystal frequency

#define TX_ATTEN_MAX                (359)                       // max tx gain

#define TDD_MODE					(0)
#define FDD_MODE					(1)

#define _ON_						(1)
#define _OFF_						(0)

uint32_t    spi_read(uint32_t reg_addr);
void        spi_write(uint32_t reg_addr, uint32_t reg_data);

#endif // __IRIS404_H__

// *
// EOF
//
